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| 1 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram ?2002, micron technology, inc. mt55l1my18f_h.p65 ? rev. h, pub. 9/02 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram products and specifications discussed herein are subject to change by micron without notice. not recommended for new designs 18mb zbt ? sram features ? high frequency and 100 percent bus utilization fast cycle times: 10ns, 11ns and 12ns single +3.3v 5%, or 2.5v 5% power supply (v dd ) separate +3.3v or +2.5v isolated output buffer supply (v dd q) advanced control logic for minimum control signal interface individual byte write controls may be tied low single r/w# (read/write) control pin cke# pin to enable clock and suspend operations three chip enables for simple depth expansion clock-controlled and registered addresses, data i/os, and control signals internally self-timed, fully coherent write internally self-timed, registered outputs to eliminate the need to control oe# snooze mode for reduced-power standby common data inputs and data outputs linear or interleaved burst modes burst feature (optional) pin and ball/function compatibility with 2mb, 4mb, and 8mb zbt sram options tqfp marking timing (access/cycle/mhz) 2.5v v dd , 2.5v i/o 7.5ns/10ns/100 mhz -10 9ns/12ns/83 mhz -12 3.3v v dd , 3.3v or 2.5v i/o 8.5ns/11ns/90 mhz -11 9ns/12ns/83 mhz -12 configurations 3.3v v dd , 3.3v or 2.5v i/o 1 meg x 18 mt55l1my18f 512k x 32 mt55l512y32f 512k x 36 mt55l512y36f 2.5v v dd , 2.5v i/o 1 meg x 18 mt55v1mv18f 512k x 32 mt55v512v32f 512k x 36 mt55v512v36f packages 100-pin tqfp t 165-ball fbga f* mt55l1my18f, mt55v1mv18f, mt55l512y32f, mt55v512v32f, mt55l512y36f, mt55v512v36f 3.3v v dd , 3.3v or 2.5v i/o; 2.5v v dd 2.5v i/o note: 1. jedec-standard ms-026 bha (lqfp). 165-ball fbga 100-pin tqfp 1 * a part marking guide for the fbga devices can be found on micron?s web site? http://www.micron.com/support/index.html. general description the micron ? zero bus turnaround ? (zbt ? ) sram family employs high-speed, low-power cmos designs using an advanced cmos process. micron?s 18mb zbt srams integrate a 1 meg x 18, 512k x 32, or 512k x 36 sram core with advanced syn- chronous peripheral circuitry and a 2-bit burst counter. these srams are optimized for 100 percent bus utiliza- tion, eliminating any turnaround cycles for read to write, or write to read, transitions. all synchronous inputs pass through registers controlled by a positive- edge-triggered single clock input (clk). the synchro- nous inputs include all addresses, all data inputs, chip enable (ce#), two additional chip enables for easy depth expansion (ce2, ce2#), cycle start input (adv/ld#), syn- chronous clock enable (cke#), byte write enables (bwa#, bwb#, bwc#, and bwd#), and read/write (r/w#). operating temperature range commercial (0oc t a +70oc) none part number example: mt55l512y32ft-12
2 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs 36 36 36 36 36 36 36 k mode 19 bwa# bwb# r/w# ce# ce2 ce2# oe# read logic dqs dqpa dqpb dqpc dqpd 512k x 8 x 4 (x32) 512k x 9 x 4 (x36) memory array e input register bwc# bwd# address register write registry and data coherency control logic 19 19 17 19 burst logic sa0' sa1' d1 d0 q1 q0 sa0 sa1 19 adv/ld# ce adv/ld# k clk cke# write drivers d a t a s t e e r i n g o u t p u t b u f f e r s e s e n s e a m p s write address register sa0, sa1, sa note: functional block diagrams illustrate simplified device operation. see truth table, pin/ball descriptions, and timing diagrams for detailed information. functional block diagram 512k x 32/36 functional block diagram 1 meg x 18 dqs dqpa dqpb 18 18 18 18 18 18 18 sa0, sa1, sa k mode 20 bwa# bwb# r/w# ce# ce2 ce2# oe# read logic d a t a s t e e r i n g o u t p u t b u f f e r s 1 meg x 9 x 2 memory array e e address register write registry and data coherency control logic 20 20 18 20 burst logic sa0' sa1' d1 d0 q1 q0 sa0 sa1 20 adv/ld# ce adv/ld# k s e n s e a m p s clk cke# write drivers write address register input register 3 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs general description (continued) asynchronous inputs include the output enable (oe#, which may be tied low for control signal minimization), clock (clk) and snooze enable (zz, which may be tied low if unused). there is also a burst mode pin/ball (mode) that selects between interleaved and linear burst modes. mode may be tied high, low or left uncon- nected if burst is unused. the flow-through data-out (q) is enabled by oe#. write cycles can be from one to four bytes wide as controlled by the write control inputs. all read, write, and deselect cycles are initiated by the adv/ld# input. subsequent burst addresses can be internally generated as controlled by the burst ad- vance pin (adv/ld#). use of burst mode is optional. it is allowable to give an address for each individual read and write cycle. burst cycles wrap around after the fourth access from a base address. to allow for continuous, 100 percent use of the data bus, the flow-through zbt sram uses a late write cycle. for example, if a write cycle begins in clock cycle one, the address is present on rising edge one. byte writes need to be asserted on the same cycle as the address. the write data associated with the address is required one cycle later, or on the rising edge of clock cycle two. address and write control are registered on-chip to simplify write cycles. this allows self-timed write cycles. individual byte enables allow individual bytes to be written. during a byte write cycle, bwa# controls dqa pins/balls; bwb# controls dqb pins/balls; bwc# controls dqc pins/balls; and bwd# controls dqd pins/ balls. cycle types can only be defined when an address is loaded, i.e., when adv/ld# is low. parity/ecc bits are only available on the x36 versions. the device is ideally suited for systems requiring high bandwidth and zero bus turnaround delays. please refer to micron?s web site ( www.micron.com/ sramds ) for the latest data sheet. dual voltage i/o the 3.3v v dd device is tested for 3.3v and 2.5v i/o function. the 2.5v v dd device is tested for only 2.5v i/o function. 4 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs pin # x18 x32 x36 1nc nf dqpc 3 2nc dqc dqc 3nc dqc dqc 4v dd q 5v ss 6nc dqc dqc 7nc dqc dqc 8 dqb dqc dqc 9 dqb dqc dqc 10 v ss 11 v dd q 12 dqb dqc dqc 13 dqb dqc dqc 14 v ss 1 15 v dd 16 v dd 2 17 v ss 18 dqb dqd dqd 19 dqb dqd dqd 20 v dd q 21 v ss 22 dqb dqd dqd 23 dqb dqd dqd 24 dqb dqd dqd 25 nc dqd dqd pin # x18 x32 x36 51 nc nf dqpa 52 nc dqa dqa 53 nc dqa dqa 54 v dd q 55 v ss 56 nc dqa dqa 57 nc dqa dqa 58 dqa 59 dqa 60 v ss 61 v dd q 62 dqa 63 dqa 64 zz 65 v dd 66 v ss 1 67 v ss 68 dqa dqb dqb 69 dqa dqb dqb 70 v dd q 71 v ss 72 dqa dqb dqb 73 dqa dqb dqb 74 dqa dqb dqb 75 nc dqb dqb pin # x18 x32 x36 76 v ss 77 v dd q 78 nc dqb dqb 79 nc dqb dqb 80 sa nf dqpb 81 sa 82 sa 83 sa 84 sa 85 adv/ld# 86 oe# (g#) 87 cke# 88 r/w# 89 clk 90 v ss 91 v dd 92 ce2# 93 bwa# 94 bwb# 95 nc bwc# bwc# 96 nc bwd# bwd# 97 ce2 98 ce# 99 sa 100 sa 26 v ss 27 v dd q 28 nc dqd dqd 29 nc dqd dqd 30 nc nf dqpd 31 mode (lbo#) 32 sa 33 sa 34 sa 35 sa 36 sa1 37 sa0 38 dnu 39 dnu 40 v ss 41 v dd 42 dnu 43 dnu 44 sa 45 sa 46 sa 47 sa 48 sa 49 sa 50 sa pin # x18 x32 x36 tqfp pin assignment table note: 1. pins 14 and 66 do not have to be connected directly to v ss if the input voltage is v il . 2. pin 16 does not have to be connected directly to v dd if the input voltage is v ih . 3. nf for x32 version, dqpx for x36 version. 5 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs pin assignment (top view) 100-pin tqfp sa sa sa sa adv/ld# oe# (g#) cke# r/w# clk v ss v dd ce2# bwa# bwb# nc nc ce2 ce# sa sa 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 sa nc nc v dd q v ss nc dqa dqa dqa v ss v dd q dqa dqa v ss v ss 2 v dd zz dqa dqa v dd q v ss dqa dqa nc nc v ss v dd q nc nc nc sa sa sa sa sa sa sa dnu dnu v dd v ss dnu dnu sa0 sa1 sa sa sa sa mode (lbo#) nc nc nc v dd q v ss nc nc dqb dqb v ss v dd q dqb dqb v ss 2 v dd v dd 3 v ss dqb dqb v dd q v ss dqb dqb dqb nc v ss v dd q nc nc nc x18 note: 1. nf for x32 version, dqpx for x36 version. 2. pins 14 and 66 do not have to be connected directly to v ss if the input voltage is v il . 3. pin 16 does not have to be connected directly to v dd if the input voltage is v ih . sa sa sa sa adv/ld# oe# (g#) cke# r/w# clk v ss v dd ce2# bwa# bwb# bwc# bwd# ce2 ce# sa sa 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 nf/ dqpb 1 dqb dqb v dd q v ss dqb dqb dqb dqb v ss v dd q dqb dqb v ss v ss 2 v dd zz dqa dqa v dd q v ss dqa dqa dqa dqa v ss v dd q dqa dqa nf/ dqpa 1 sa sa sa sa sa sa sa dnu dnu v dd v ss dnu dnu sa0 sa1 sa sa sa sa mode (lbo#) nf/ dqpc 1 dqc dqc v dd q v ss dqc dqc dqc dqc v ss v dd q dqc dqc v ss 2 v dd v dd 3 v ss dqd dqd v dd q v ss dqd dqd dqd dqd v ss v dd q dqd dqd nf/ dqpd 1 x32/x36 6 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs tqfp pin descriptions x18 x32/36 symbol type description 37 37 sa0 input synchronous address inputs: these inputs are registered 36 36 sa1 and must meet the setup and hold times around the 32?35, 44?50, 32?35, 44?50, sa rising edge of clk. sa0 and sa1 are the two least 80?84, 99, 81?84, 99, significant bits (lsb) of the address field and set the 100 100 internal burst counter if burst is desired. 93 93 bwa# input synchronous byte write enables: these active low 94 94 bwb# inputs allow individual bytes to be written when a ? 95 bwc# write cycle is active and must meet the setup and hold ? 96 bwd# times around the rising edge of clk. byte writes need to be asserted on the same cycle as the address. bwa# controls dqa pins; bwb# controls dqb pins; bwc# controls dqc pins; bwd# controls dqd pins. 89 89 clk input clock: this signal registers the address, data, chip enables, byte write enables, and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock?s rising edge. 98 98 ce# input synchronous chip enable: this active low input is used to enable the device and is sampled only when a new external address is loaded (adv/ld# low). 92 92 ce2# input synchronous chip enable: this active low input is used to enable the device and is sampled only when a new external address is loaded (adv/ld# low). this input can be used for memory depth expansion. 97 97 ce2 input synchronous chip enable: this active high input is used to enable the device and is sampled only when a new external address is loaded (adv/ld# low). this input can be used for memory depth expansion. 86 86 oe# input output enable: this active low, asynchronous input (g#) enables the data i/o output drivers. g# is the jedec- standard term for oe#. 85 85 adv/ld# input synchronous address advance/load: when high, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. when adv/ld# is high, r/w# is ignored. a low on adv/ld# clocks a new address at the clk rising edge. 87 87 cke# input synchronous clock enable: this active low input permits clk to propagate throughout the device. when cke is high, the device ignores the clk input and effectively internally extends the previous clk cycle. this input must meet setup and hold times around the rising edge of clk. 64 64 zz input snooze enable: this active high, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. when zz is active, all other inputs are ignored. this pin has an internal pull-down and can be floating. (continued on next page) 7 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs tqfp pin descriptions (continued) x18 x32/36 symbol type description 88 88 r/w# input read/write: this input determines the cycle type when adv/ld# is low and is the only means for determining reads and writes. read cycles may not be converted into writes (and vice versa) other than by loading a new address. a low on this pin permits byte write operations and must meet the setup and hold times around the rising edge of clk. full bus-width writes occur if all byte write enables are low. 31 31 mode input mode: this input selects the burst sequence. a low on (lbo#) this pin selects linear burst. nc or high on this pin selects interleaved burst. do not alter input state while device is operating. lbo# is the jedec-standard term for mode. (a) 58, 59, 62, 63, (a) 52, 53, 56?59, dqa input/ sram data i/os: byte ?a? is associated with dqa pins; 68, 69, 72?74 62, 63 output byte ?b? is associated with dqb pins; byte ?c? is (b) 8, 9, 12, 13, (b) 68, 69, 72?75, dqb associated with dqc pins; byte ?d? is associated with 18, 19, 22?24 78, 79 dqd pins. input data must meet setup and hold times (c) 2, 3, 6?9, dqc around the rising edge clk. 12, 13 (d) 18, 19, 22?25, dqd 28, 29 ? 51 nf/ dqpa nf/ no function/data bits: on the x32 version, these pins are ? 80 nf/ dqpb i/o no function (nf) and can be left floating or connected 1 nf/ dqpc to gnd to minimize thermal impedance. on the x36 30 nf/ dqpd version, these bits are dqs. no function balls are internally connected to the die and have the capacitance of an input pin. it is allowable to leave these pins unconnected or driven by signals. 15, 16, 41, 65, 91 15, 16, 41, 65, 91 v dd supply power supply: see dc electrical characteristics and operating conditions for range. 4, 11, 20, 27, 4, 11, 20, 27, v dd q supply isolated output buffer supply: see dc electrical 54, 61, 70, 77 54, 61, 70, 77 characteristics and operating conditions for range. 5, 10, 14, 17, 21, 5, 10, 14, 17, 21, v ss supply ground: gnd. 26, 40, 55, 60, 26, 40, 55, 60, 66, 67, 71, 76, 90 66, 67, 71, 76, 90 1?3, 6, 7, 25, ? nc ? no connect: these pins can be left floating or connected 28?30, 51?53, 56, to gnd to minimize thermal impedance. 57, 75, 78, 79, 95, 96 38, 39, 42, 43 38, 39, 42, 43 dnu ? do not use: these signals may either be unconnected or wired to gnd to minimize thermal impedance. 8 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs ball layout (top view) 165-ball fbga a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 2 ce# ce2 v dd q v dd q v dd q v dd q v dd q nc v dd q v dd q v dd q v dd q v dd q sa sa sa sa nc dqb dqb dqb dqb v dd nc nc nc nc nc nc nc nc nc nc nc nc nc nc v ss dqb dqb dqb dqb dqpb nc mode (lbo#) bwb# nc v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss sa sa nc bwa# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss nc tdi tms ce2# clk v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss nc sa1 sa0 cke# r/w# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss tdo tck adv/ld# oe# (g#) v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss sa sa sa sa v dd q v dd q v dd q v dd q v dd q nc v dd q v dd q v dd q v dd q v dd q sa sa sa sa nc nc nc nc nc nc dqa dqa dqa dqa nc sa sa sa nc dqpa dqa dqa dqa dqa zz nc nc nc nc nc nc sa top view 3456789 10 11 1 a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 2 ce# ce2 v dd q v dd q v dd q v dd q v dd q nc v dd q v dd q v dd q v dd q v dd q sa sa sa sa nc dqc dqc dqc dqc v dd dqd dqd dqd dqd nc nc nc nc nc nf/ dqpc dqc dqc dqc dqc v ss dqd dqd dqd dqd nf/ dqpd nc mode (lbo#) bwc# bwd# v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss sa sa bwb# bwa# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss nc tdi tms ce2# clk v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss nc sa1 sa0 cke# r/w# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss tdo tck adv/ld# oe# (g#) v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss sa sa sa sa v dd q v dd q v dd q v dd q v dd q nc v dd q v dd q v dd q v dd q v dd q sa sa sa sa nc dqb dqb dqb dqb nc dqa dqa dqa dqa nc sa sa nc nc nf/ dqpb dqb dqb dqb dqb zz dqa dqa dqa dqa nf /dqpa nc sa top view 3456789 10 11 1 x18 x32/x36 *no function (nf) is used on the x32 version. parity (dqpx) is used on the x36 version. 9 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs fbga ball descriptions x18 x32/x36 symbol type description 6r 6r sa0 input synchronous address inputs: these inputs are registered and 6p 6p sa1 must meet the setup and hold times around the rising edge of 2a, 2b, 3p, 2a, 2b, 3p, sa clk. 3r, 4p, 4r, 3r, 4p, 4r, 8p, 8r, 9a, 8p, 8r, 9a, 9b, 9p, 9r, 9b, 9p, 9r, 10a, 10b, 10p,10a, 10b, 10p, 10r, 11a, 11r 10r, 11r 5b 5b bwa# input synchronous byte write enables: these active low inputs allow 4a 5a bwb# individual bytes to be written and must meet the setup and hold ? 4a bwc# times around the rising edge of clk. a byte write enable is low ? 4b bwd# for a write cycle and high for a read cycle. for the x18 version, bwa# controls dqa balls and dqpa; bwb# controls dqb balls and dqpb. for the x32 and x36 versions, bwa# controls dqa balls and dqpa; bwb# controls dqb balls and dqpb; bwc# controls dqc balls and dqpc; bwd# controls dqd balls and dqpd. parity is only available on the x18 and x36 versions. 7a 7a cke# input synchronous clock enable: this active low input permits clk to propogate throughout the device. when cke# is high, the device ignores the clk input and effectively internally extends the previous clk cycle. this input must meet the setup and hold times around the rising edge of clk. 7b 7b r/w# input read/write: this input determines the cycle type when adv/ld# is low and is the only means for determining reads and writes. read cycles may not be converted into writes (and vice versa) other than by loading a new address. a low on this ball permits byte write operations to meet the setup and hold times around the rising edge of clk. full bus-width writes occur if all byte write enables are low. 6b 6b clk input clock: this signal registers the address, data, chip enable, byte write enables, and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock?s rising edge. 3a 3a ce# input synchronous chip enable: this active low input is used to enable the device. ce# is sampled only when a new external address is loaded. (adv/ld# low) 6a 6a ce2# input synchronous chip enable: this active low input is used to enable the device and is sampled only when a new external address is loaded. 11h 11h zz input snooze enable: this active high, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. when zz is active, all other inputs are ignored. 3b 3b ce2 input synchronous chip enable: this active high input is used to enable the device and is sampled only when a new external address is loaded. (continued on next page) 10 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs fbga ball descriptions (continued) x18 x32/x36 symbol type description 8b 8b oe#(g#) input output enable: this active low, asynchronous input enables the data i/o output drivers. 8a 8a adv/ld# input synchronous address advance/load: when high, this input is used to advance the internal burst counter, controlling burst access after the external address is loaded. when adv/ld# is high, r/w# is ingored. a low on adv/ld# clocks a new address at the clk rising edge. 1r 1r mode input mode: this input selects the burst sequence. a low on this input (lb0#) selects ?linear burst.? nc or high on this input selects ?interleaved burst.? do not alter input state while device is operating. 5r 5r tms input ieee 1149.1 test inputs: jedec-standard 2.5v i/o levels. these balls 5p 5p tdi may be left not connected if the jtag function is not used in the 7r 7r tck circuit. (a) 10j, 10k, (a) 10j, 10k, dqa input/ sram data i/os: for the x18 version, byte ?a? is associated with 10l, 10m, 11d, 10l, 10m, 11j, output dqa balls; byte ?b? is associated with dqb balls. for the x32 and 11e, 11f, 11g 11k, 11l, 11m x36 versions, byte ?a? is associated with dqa balls; byte ?b? is (b) 1j, 1k, (b) 10d, 10e, dqb associated with dqb balls; byte ?c? is associated with dqc balls; 1l, 1m, 2d, 10f, 10g, 11d, byte ?d? is associated with dqd balls. input data must meet setup 2e, 2f, 2g 11e, 11f, 11g and hold times around the rising edge of clk. (c) 1d, 1e, dqc 1f, 1g, 2d, 2e, 2f, 2g (d) 1j, 1k, 1l, dqd 1m, 2j, 2k, 2l, 2m 11c 11n nf/ dqpa nc/ no function/parity data i/os: on the x32 version, these are no 1n 11c nf/ dqpb i/o function (nf). on the x18 version, byte ?a? parity is dqpa; byte ?b? ? 1c nf/ dqpc parity is dqpb. on the x36 version, byte ?a? parity is dqpa; byte ? 1n nf/ dqpd ?b? parity is dqpb; byte ?c? parity is dqpc; byte ?d? parity is dqpd. no function balls are internally connected to the die and have the capacitance of an input pin. it is allowable to leave these balls unconnected or driven by signals. 2h, 4d, 4e, 4f, 2h, 4d, 4e, 4f, v dd supply power supply: see dc electrical characteristics and operating 4g, 4h, 4j, 4g, 4h, 4j, conditions for range. 4k, 4l, 4m, 4k, 4l, 4m, 8d, 8e, 8f, 8d, 8e, 8f, 8g, 8h, 8j, 8g, 8h, 8j, 8k, 8l, 8m 8k, 8l, 8m 3c, 3d, 3e, 3c, 3d, 3e, v dd q supply isolated output buffer supply: see dc electrical characteristics and 3f, 3g, 3j, 3f, 3g, 3j, operating conditions for range. 3k, 3l, 3m, 3k, 3l, 3m, 3n, 9c, 9d, 3n, 9c, 9d, 9e, 9f, 9g, 9e, 9f, 9g, 9j, 9k, 9l, 9j, 9k, 9l, 9m, 9n 9m, 9n (continued on next page) 11 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs fbga ball descriptions (continued) x18 x32/x36 symbol type description 1h, 4c, 4n, 1h, 4c, 4n, v ss supply ground: gnd. 5c, 5d, 5e, 5f, 5c, 5d, 5e, 5f, 5g, 5h, 5j, 5g, 5h, 5j, 5k, 5l, 5m, 5k, 5l, 5m, 6c, 6d, 6e, 6f, 6c, 6d, 6e, 6f, 6g, 6h, 6j, 6g, 6h, 6j, 6k, 6l, 6m, 6k, 6l, 6m, 7c, 7d, 7e, 7c, 7d, 7e, 7f, 7g, 7h, 7f, 7g, 7h, 7j, 7k, 7l, 7j, 7k, 7l, 7m, 7n, 8c, 8n 7m, 7n, 8c, 8n 7p 7p tdo output ieee 1149.1 test output: jedec-standard 2.5v i/o level. 1a, 1b, 1c, 1a, 1b, 1p, nc ? no connect: these signals are not internally connected and may 1d, 1e, 1f, 2c, 2n, 2p, be connected to ground to improve package heat dissipation. 1g, 1p, 2c, 2r, 3h, 5n, 2j, 2k, 2l, 6n, 9h, 10c, 2m, 2n, 2p, 10h, 10n, 2r, 3h, 4b, 11a, 11b, 5a, 5n, 6n, 11p 9h, 10c, 10d, 10e, 10f, 10g, 10h, 10n, 11b, 11j, 11k, 11l, 11m, 11n, 11p 12 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs function r/w# bwa# bwb# bwc# bwd# read h x x x x write byte ?a? l l h h h write byte ?b? l h l h h write byte ?c? l h h l h write byte ?d? l h h h l write all bytes l l l l l write abort/nop l h h h h function r/w# bwa# bwb# read h x x write byte ?a? l l h write byte ?b? l h l write all bytes l l l write abort/nop l h h interleaved burst address table (mode = nc or high) first address (external) second address (internal) third address (internal) fourth address (internal) x...x00 x...x01 x...x10 x...x11 x...x01 x...x00 x...x11 x...x10 x...x10 x...x11 x...x00 x...x01 x...x11 x...x10 x...x01 x...x00 linear burst address table (mode = low) first address (external) second address (internal) third address (internal) fourth address (internal) x...x00 x...x01 x...x10 x...x11 x...x01 x...x10 x...x11 x...x00 x...x10 x...x11 x...x00 x...x01 x...x11 x...x00 x...x01 x...x10 partial truth table for read/write commands (x18) note: using r/w# and byte write(s), any one or more bytes may be written. note: using r/w# and byte write(s), any one or more bytes may be written. partial truth table for read/write commands (x32/x36) 13 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs state diagram for zbt sram deselect begin read burst read begin write ds ds ds burst write read ds write write burst read write read burst burst read burst ds write key: command ds read write burst operation deselect new read new write burst read, burst write, or continue deselect burst read write note: 1. a stall or ignore clock edge cycle is not shown in the above diagram. this is because cke# high only blocks the clock (clk) input and does not change the state of the device. 2. states change on the rising edge of the clock (clk). 14 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs truth table (notes 5-10) address adv/ operation used ce# ce2# ce2 zz ld# r/w# bwx oe# cke# clk dq notes deselect cycle none h x x l l x x x l l h high-z deselect cycle none x h x l l x x x l l h high-z deselect cycle none x x l l l x x x l l h high-z continue deselect cycle none x x x l h x x x l l h high-z 1 read cycle external l l h l l h x l l l hq (begin burst) read cycle next x x x l h x x l l l h q 1, 11 (continue burst) nop/dummy read external l l h l l h x h l l h high-z 2 (begin burst) dummy read next x x x l h x x h l l h high-z 1, 2, (continue burst) 11 write cycle external l l h l l l l x l l hd 3 (begin burst) write cycle next x x x l h x l x l l h d 1, 3, (continue burst) 11 nop/write abort none l l h l l l h x l l h high-z 2, 3 (begin burst) write abort next x x x l h x h x l l h high-z 1, 2, (continue burst) 3, 11 ignore clock edge current x x x l x x x x h l h? 4 (stall) snooze mode none x x x h x x x x x x high-z note: 1. continue burst cycles, whether read or write, use the same control inputs. the type of cycle performed (read or write) is chosen in the initial begin burst cycle. a continue deselect cycle can only be entered if a deselect cycle is executed first. 2. dummy read and write abort cycles can be considered nops because the device performs no external operation. a write abort means a write command is given, but no operation is performed. 3. oe# may be wired low to minimize the number of control signals to the sram. the device will automatically turn off the output drivers during a write cycle. oe# may be used when the bus turn-on and turn-off times do not meet an application?s requirements. 4. if an ignore clock edge command occurs during a read operation, the dq bus will remain active (low-z). if it occurs during a write cycle, the bus will remain in high-z. no write operations will be performed during the ignore clock edge cycle. 5. x means ?don?t care.? h means logic high. l means logic low. bwx = h means all byte write signals (bwa#, bwb#, bwc#, and bwd#) are high. bwx = l means one or more byte write signals are low. 6. bwa# enables writes to byte ?a? (dqa pins); bwb# enables writes to byte ?b? (dqb pins); bwc# enables writes to byte ?c? (dqc pins); bwd# enables writes to byte ?d? (dqd pins). 7. all inputs except oe# and zz must meet setup and hold times around the rising edge (low to high) of clk. 8. wait states are inserted by setting cke# high. 9. this device contains circuitry that will ensure that the outputs will be in high-z during power-up. 10. the device incorporates a 2-bit burst counter. address wraps to the initial address every fourth burst cycle. 11. the address counter is incremented for all continue burst cycles. 15 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs 3.3v v dd , absolute maximum ratings* voltage on v dd supply relative to v ss ........................................ -0.5v to +4.6v voltage on v dd q supply relative to v ss ........................................... -0.5v to v dd v in (dqs) ........................................... -0.5v to v dd q + 0.5v v in (inputs) ........................................... -0.5v to v dd + 0.5v storage temperature (tqfp) ................ -55oc to +150oc storage temperature (fbga) ................ -55oc to +125oc junction temperature** ......................................... +150oc short circuit output current ................................ 100ma 2.5v v dd , absolute maximum ratings* voltage on v dd supply relative to v ss ........................................................ -0.3v to +3.6v voltage on v dd q supply relative to v ss ........................................................ -0.3v to +3.6v v in (dqs) ........................................... -0.3v to v dd q + 0.3v v in (inputs) ........................................... -0.3v to v dd + 0.3v storage temperature (tqfp) ................ -55oc to +150oc storage temperature (fbga) ................ -55oc to +125oc junction temperature** ........................................ +150oc short circuit output current ................................ 100ma *stresses greater than those listed under ?absolute maxi- mum ratings? may cause permanent damage to the de- vice. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. **junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow. see micron technical note tn-05-14 for more information. 3.3v v dd , 3.3v i/o dc electrical characteristics and operating conditions (0oc a + 70oc; v dd , v dd q = +3.3v 0.165v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage v ih 2.0 v dd + 0.3 v 1, 2 input high (logic 1) voltage dq pins/balls v ih 2.0 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.8 v 1, 2 input leakage current 0v v in v dd il i -1.0 1.0 a 3 output leakage current output(s) disabled, il o -1.0 1.0 a 0v v in v dd output high voltage i oh = -4.0ma v oh 2.4 v 1, 4 output low voltage i ol = 8.0ma v ol 0.4 v 1, 4 supply voltage v dd 3.135 3.465 v 1 isolated output buffer supply v dd q 3.135 v dd v 1, 5 note: 1. all voltages referenced to v ss (gnd). 2. for 3.3v v dd : overshoot: v ih +4.6v for t t khkh/2 for i 20ma undershoot: v il -0.7v for t t khkh/2 for i 20ma power-up: v ih +3.6v and v dd 3.135v for t 200ms for 2.5v v dd : overshoot: v ih +3.6v for t t khkh/2 for i 20ma undershoot: v il -0.5v for t t khkh/2 for i 20ma power-up: v ih +2.65v and v dd 2.375v for t 200ms 3. mode pin has an internal pull-up, and input leakage = 10a. 4. the load used for v oh , v ol testing is shown in figure 2. ac load current is higher than the shown dc values. ac i/o curves are available upon request. 5. v dd q should never exceed v dd . v dd and v dd q can be externally wired together to the same power supply. 16 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs 3.3v v dd , 2.5v i/o dc electrical characteristics and operating conditions (0oc t a + 70oc; v dd = +3.3v 0.165v; v dd q = +2.5v 0.125v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage data bus (dqx) v ih q1.7v dd q + 0.3 v 1, 2 inputs v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -1.0 1.0 a 3 output leakage current output(s) disabled, il o -1.0 1.0 a 0v v in v dd q (dqx) output high voltage i oh = -2.0ma v oh 1.7 ? v 1 i oh = -1.0ma v oh 2.0 ? v 1 output low voltage i ol = 2.0ma v ol ?0.7v1 i ol = 1.0ma v ol ?0.4v1 supply voltage v dd 3.135 3.465 v 1 isolated output buffer supply v dd q 2.375 2.625 v 1 2.5v v dd , 2.5v i/o dc electrical characteristics and operating conditions (0oc t a + 70oc; v dd = +2.5v 0.125v; v dd q = +2.5v 0.125v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage data bus (dqx) v ih q1.7v dd q + 0.3 v 1, 2 inputs v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -1.0 1.0 a 3 output leakage current output(s) disabled, il o -1.0 1.0 a 0v v in v dd q (dqx) output high voltage i oh = -2.0ma v oh 1.7 ? v 1 i oh = -1.0ma v oh 2.0 ? v 1 output low voltage i ol = 2.0ma v ol ?0.7v1 i ol = 1.0ma v ol ?0.4v1 supply voltage v dd 2.375 2.625 v 1 isolated output buffer supply v dd q 2.375 2.625 v 1 note: 1. all voltages referenced to v ss (gnd). 2. for 3.3v v dd : overshoot: v ih +4.6v for t t khkh/2 for i 20ma undershoot: v il -0.7v for t t khkh/2 for i 20ma power-up: v ih +3.6v and v dd 3.135v for t 200ms for 2.5v v dd : overshoot: v ih +3.6v for t t khkh/2 for i 20ma undershoot: v il -0.5v for t t khkh/2 for i 20ma power-up: v ih +2.65v and v dd 2.375v for t 200ms 3. mode pin has an internal pull-up, and input leakage = 10a. 17 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs tqfp capacitance description conditions symbol typ max units notes control input capacitance t a = 25oc; f = 1 mhz c i 4.8 6.0 pf 1 input/output capacitance (dq) v dd = 3.3v c o 3.8 4.5 pf 1 address capacitance c a 4.7 5.5 pf 1 clock capacitance c ck 4.5 5.0 pf 1 fbga capacitance description conditions symbol typ max units notes address/control input capacitance c i 2.5 3.5 pf 1 output capacitance (q) t a = 25oc; f = 1 mhz c o 45pf1 clock capacitance c ck 2.5 3.5 pf 1 note: 1. this parameter is sampled. tqfp thermal resistance description conditions symbol typ units notes thermal resistance test conditions follow standard test methods ja 46 oc/w 1 (junction to ambient) and procedures for measuring thermal thermal resistance impedance, per eia/jesd51. jc 2.8 oc/w 1 (junction to top of case) fbga thermal resistance description conditions symbol typ units notes junction to ambient test conditions follow standard test methods ja 40 oc/w 1 (airflow of 1m/s) and procedures for measuring thermal junction to case (top) impedance, per eia/jesd51. jc 9 oc/w 1 junction to pins/balls jb 17 oc/w 1 (bottom) 18 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs max 3.3v v dd , i dd operating conditions and maximum limits (512k x 32/36) (note 1, unless otherwise noted) (0oc t a + 70oc) description conditions symbol typ -11 -12 units notes power supply device selected; all inputs v il or v ih ; current: operating cycle time t kc (min); i dd tbd 480 450 ma 2, 3, 4 v dd = max; outputs open power supply device selected; v dd = max; current: idle cke# v ih ;i dd 1 tbd 160 150 ma 2, 3, 4 all inputs v ss + 0.2 or v dd - 0.2; cycle time t kc (min) cmos standby device deselected; v dd = max; all inputs v ss + 0.2 or v dd - 0.2; i sb 2 tbd 30 30 ma 3, 4 all inputs static; clk frequency = 0 ttl standby device deselected; v dd = max; all inputs v il or v ih ;i sb 3 tbd 100 100 ma 3, 4 all inputs static; clk frequency = 0 clock running device deselected; v dd = max; adv/ld# v ih ; all inputs v ss + 0.2 i sb 4 tbd 160 150 ma 3, 4 or v dd - 0.2; cycle time t kc (min) snooze mode zz v ih i sb 2 z tbd 10 10 ma 4 note: 1. v dd q = +3.3v or +2.5v. voltage tolerances: +3.3v 0.165 or +2.5v 0.125v for all values of v dd and v dd q. 2. i dd is specified with no output current and increases with faster cycle times. i dd q increases with faster cycle times and greater output loading. 3. ?device deselected? means device is in a deselected cycle as defined in the truth table. ?device selected? means device is active (not in deselected mode). 4. typical values are measured at 3.3v, 25oc, and 12ns cycle time. 19 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs max 2.5v v dd , i dd operating conditions and maximum limits (512k x 32/36) (note 1, unless otherwise noted) (0oc t a + 70oc) description conditions symbol typ -10 -12 units notes power supply device selected; all inputs v il or v ih ; current: operating cycle time t kc (min); i dd tbd 400 345 ma 2, 3, 4 v dd = max; outputs open power supply device selected; v dd = max; current: idle cke# v ih ;i dd 1 tbd 135 115 ma 2, 3, 4 all inputs v ss + 0.2 or v dd - 0.2; cycle time t kc (min) cmos standby device deselected; v dd = max; all inputs v ss + 0.2 or v dd - 0.2; i sb 2 tbd 225 25 ma 3, 4 all inputs static; clk frequency = 0 ttl standby device deselected; v dd = max; all inputs v il or v ih ;i sb 3 tbd 80 80 ma 3, 4 all inputs static; clk frequency = 0 clock running device deselected; v dd = max; adv/ld# v ih ; all inputs v ss + 0.2 i sb 4 tbd 135 115 ma 3, 4 or v dd - 0.2; cycle time t kc (min) snooze mode zz v ih i sb 2 z tbd 10 10 ma 4 note: 1. v dd q = +2.5v. voltage tolerances: +3.3v 0.165 or +2.5v 0.125v for all values of v dd and v dd q. 2. i dd is specified with no output current and increases with faster cycle times. i dd q increases with faster cycle times and greater output loading. 3. ?device deselected? means device is in a deselected cycle as defined in the truth table. ?device selected? means device is active (not in deselected mode). 4. typical values are measured at 2.5v, 25oc, and 12ns cycle time. 20 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs max 3.3v v dd , i dd operating conditions and maximum limits (1 meg x 18) (note 1, unless otherwise noted) (0oc t a + 70oc) description conditions symbol typ -11 -12 units notes power supply device selected; all inputs v il or v ih ; current: operating cycle time t kc (min); i dd tbd 360 340 ma 2, 3, 4 v dd = max; outputs open power supply device selected; v dd = max; current: idle cke# v ih ;i dd 1 tbd 120 115 ma 2, 3, 4 all inputs v ss + 0.2 or v dd - 0.2; cycle time t kc (min) cmos standby device deselected; v dd = max; all inputs v ss + 0.2 or v dd - 0.2; i sb 2 tbd 25 25 ma 3, 4 all inputs static; clk frequency = 0 ttl standby device deselected; v dd = max; all inputs v il or v ih ;i sb 3 tbd 75 75 ma 3, 4 all inputs static; clk frequency = 0 clock running device deselected; v dd = max; adv/ld# v ih ; all inputs v ss + 0.2 i sb 4 tbd 120 115 ma 3, 4 or v dd - 0.2; cycle time t kc (min) snooze mode zz v ih i sb 2 z tbd 10 10 ma 4 note: 1. v dd q = +3.3v or +2.5v. voltage tolerances: +3.3v 0.165 or +2.5v 0.125v for all values of v dd and v dd q. 2. i dd is specified with no output current and increases with faster cycle times. i dd q increases with faster cycle times and greater output loading. 3. ?device deselected? means device is in a deselected cycle as defined in the truth table. ?device selected? means device is active (not in deselected mode). 4. typical values are measured at 3.3v, 25oc, and 12ns cycle time. 21 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs max 2.5v v dd , i dd operating conditions and maximum limits (1 meg x 18) (note 1, unless otherwise noted) (0oc t a + 70oc) description conditions symbol typ -10 -12 units notes power supply device selected; all inputs v il current: operating or v ih ; cycle time t kc (min); i dd tbd 305 260 ma 2, 3, 4 v dd = max; outputs open power supply device selected; v dd = max; current: idle cke# v ih ;i dd 1 tbd 105 90 ma 2, 3, 4 all inputs v ss + 0.2 or v dd - 0.2; cycle time t kc (min) cmos standby device deselected; v dd = max; all inputs v ss + 0.2 or v dd - 0.2; i sb 2 tbd 20 20 ma 3, 4 all inputs static; clk frequency = 0 ttl standby device deselected; v dd = max; all inputs v il or v ih ;i sb 3 tbd 80 80 ma 3, 4 all inputs static; clk frequency = 0 clock running device deselected; v dd = max; adv/ld# v ih ; all inputs v ss + 0.2 i sb 4 tbd 105 90 ma 3, 4 or v dd - 0.2; cycle time t kc (min) snooze mode zz v ih i sb 2 z tbd 10 10 ma 4 note: 1. v dd q = +2.5v. voltage tolerances: +3.3v 0.165 or +2.5v 0.125v for all values of v dd and v dd q. 2. i dd is specified with no output current and increases with faster cycle times. i dd q increases with faster cycle times and greater output loading. 3. ?device deselected? means device is in a deselected cycle as defined in the truth table. ?device selected? means device is active (not in deselected mode). 4. typical values are measured at 2.5v, 25oc, and 12ns cycle time. 22 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs note: 1. oe# can be considered a ?don?t care? during writes; however, controlling oe# can help fine-tune a system for turnaround timing. 2. test conditions as specified with the output loading shown in figure 1 for 3.3v i/o (v dd q = +3.3v 0.165v) and figure 3 for 2.5v i/o (v dd q = +2.5v +0.4v/-0.125v) unless otherwise noted. 3. a write cycle is defined by r/w# low having been registered into the device at adv/ld# low. a read cycle is defined by r/w# high with adv/ld# low. both cases must meet setup and hold times. 4. if v dd = +3.3v, then v dd q = +3.3v or +2.5v. if v dd = +2.5v, then v dd q = +2.5v. voltage tolerances: +3.3v 0.165 or +2.5v 0.125v for all values of v dd and v dd q. 5. the -10 speed grade is available for 2.5v v dd and i/o only. 6. the -11 speed grade is available for 3.3v v dd and i/o only. 7. measured as high above v ih and low below v il . 8. refer to technical note tn-55-01, ?designing with zbt srams,? for a more thorough discussion of these parameters. 9. this parameter is sampled. 10. this parameter is measured with the output loading shown in figure 2 for 3.3v i/o and figure 4 for 2.5v i/o. 11. transition is measured 200mv from steady state voltage. 12. this is a synchronous device. all addresses must meet the specified setup and hold times for all rising edges of clk when they are being registered into the device. all other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (clk) when the chip is enabled. chip enable must be valid at each rising edge of clk when adv/ld# is low to remain enabled. ac electrical characteristics (notes 1, 2, 3) (0oc t a + 70oc)(note 4, unless otherwise noted) -10 5 -11 6 -12 description symbol min max min max min max units notes clock clock cycle time t khkh 10 11 12 ns clock frequency f kf 100 90 83 mhz clock high time t khkl 2.5 3.0 3.0 ns 7 clock low time t klkh 2.5 3.0 3.0 ns 7 output times clock to output valid t khqv 7.5 8.5 9.0 ns clock to output invalid t khqx 3.0 3.0 3.0 ns 8 clock to output in low-z t khqx1 3.0 3.0 3.0 ns 8, 9, 10, 11 clock to output in high-z t khqz 5.0 5.0 5.0 ns 8, 9, 10, 11 oe# to output valid t glqv 5.0 5.0 5.0 ns 1 oe# to output in low-z t glqx 0 0 0 ns 8, 9, 10, 11 oe# to output in high-z t ghqz 5.0 5.0 5.0 ns 8, 9, 10, 11 setup times address t avkh 2.0 2.0 2.0 ns 12 clock enable (cke#) t evkh 2.0 2.0 2.0 ns 12 control signals t cvkh 2.0 2.0 2.0 ns 12 data-in t dvkh 2.0 2.0 2.0 ns 12 hold times address t khax 0.5 0.5 0.5 ns 12 clock enable (cke#) t khex 0.5 0.5 0.5 ns 12 control signals t khcx 0.5 0.5 0.5 ns 12 data-in t khdx 0.5 0.5 0.5 ns 12 23 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs q 50 ? v = 1.5v z = 50 ? o t figure 1 q 351 317 5pf +3.3v figure 2 3.3v v dd , 3.3v i/o ac test conditions input pulse levels ................................... v ss to 3.3v input rise and fall times ..................................... 1ns input timing reference levels .......................... 1.5v output reference levels ................................... 1.5v output load ............................. see figures 1 and 2 load derating curves micron 1 meg x 18, 512k x 32, and 512k x 36 zbt sram timing is dependent upon the capacitive loading on the outputs. consult the factory for copies of i/o current versus voltage curves. q 50 ? v = 1.25v z = 50 ? o t figure 3 q 225 ? 225 ? 5pf +2.5v figure 4 3.3v i/o output load equivalents 2.5v i/o output load equivalents 3.3v v dd , 2.5v i/o ac test conditions input pulse levels ................................... v ss to 2.5v input rise and fall times ..................................... 1ns input timing reference levels ........................ 1.25v output reference levels ................................. 1.25v output load ............................. see figures 3 and 4 2.5v v dd , 2.5v i/o ac test conditions input pulse levels ................................... v ss to 2.5v input rise and fall times ..................................... 1ns input timing reference levels ........................ 1.25v output reference levels ................................. 1.25v output load ............................. see figures 3 and 4 24 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs snooze mode snooze mode is a low-current, ?power-down? mode in which the device is deselected and current is reduced to i sb 2 z . the duration of snooze mode is dictated by the length of time the zz pin is in a high state. after the device enters snooze mode, all inputs except zz be- come disabled and all outputs go to high-z. the zz pin is an asynchronous, active high input that causes the device to enter snooze mode. when the zz pin becomes a logic high, i sb 2 z is guaranteed after the time t zzi is met. any read or write operation pending when the device enters snooze mode is not guaranteed to complete successfully. therefore, snooze mode must not be initiated until valid pending opera- tions are completed. similarly, when exiting snooze mode during t rzz, only a deselect or read cycle should be given. snooze mode electrical characteristics description conditions symbol min max units notes current during snooze mode zz v ih i sb 2z 10 ma zz active to input ignored t zz 0 t khkh ns 1 zz inactive to input sampled t rzz 0 t khkh ns 1 zz active to snooze current t zzi t khkh ns 1 zz inactive to exit snooze current t rzzi 0 ns 1 snooze mode waveform t zz i supply clk zz t rzz all inputs (except zz) don?t care i isb2z t zzi t rzzi outputs (q) high-z deselect or read only note: 1. this parameter is sampled. 25 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs read/write timing write d(a1) 123 456789 clk t khkh t klkh t khkl 10 ce# t khcx t cvkh r/w# cke# t khex t evkh bwx# adv/ld# t khax t avkh address a1 a2 a3 a4 a5 a6 a7 t khdx t dvkh dq command t khqx1 d(a1) d(a2) q(a4) q(a3) d(a2+1) t khqx t khqz t khqv write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe# t glqv t glqx t ghqz don?t care undefined d(a5) t khqx q(a4+1) d(a7) q(a6) note: 1. for this waveform, zz is tied low. 2. burst sequence order is determined by mode (0 = linear, 1 = interleaved). burst operations are optional. 3. ce# represents three signals. when ce# = 0, it represents ce# = 0, ce2# = 0, ce2 = 1. 4. data coherency is provided for all possible operations. if a read is initiated, the most current data is used. the most recent data may be from the input data register. -10* -11** -12 symbol min max min max min max units t ghqz 5.0 5.0 5.0 ns t avkh 2.0 2.2 2.5 ns t evkh 2.0 2.2 2.5 ns t cvkh 2.0 2.2 2.5 ns t dvkh 2.0 2.2 2.5 ns t khax 0.5 0.5 0.5 ns t khex 0.5 0.5 0.5 ns t khcx 0.5 0.5 0.5 ns t khdx 0.5 0.5 0.5 ns read/write timing parameters -10* -11** -12 symbol min max min max min max units t khkh 10 11 12 ns f kf 100 90 83 mhz t khkl 2.5 3.0 3.0 ns t klkh 2.5 3.0 3.0 ns t khqv 7.5 8.5 9.0 ns t khqx 3.0 3.0 3.0 ns t khqx1 3.0 3.0 3.0 ns t khqz 5.0 5.0 5.0 ns t glqv 5.0 5.0 5.0 ns t glqx 0 0 0 ns *the -10 speed grade available for 2.5v v dd and i/o only. **the -11 speed grade available for 3.3v v dd and i/o only. 26 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs nop, stall, and deselect cycles read q(a3) 456 78910 a3 a4 a5 d(a4) 123 clk ce# r/w# cke# bwx# adv/ld# address dq command write d(a4) stall write d(a1) read q(a2) stall nop read q(a5) deselect continue deselect don?t care undefined t khqz a1 a2 q(a2) d(a1) q(a3) t khqx q(a5) note: 1. the ignore clock edge or stall cycle (clock 3) illustrates cke# being used to create a ?pause.? a write is not performed during this cycle. 2. for this waveform, zz and oe# are tied low. 3. ce# represents three signals. when ce# = 0, it represents ce# = 0, ce2# = 0, ce2 = 1. 4. data coherency is provided for all possible operations. if a read is initiated, the most current data is used. the most recent data may be from the input data register. nop, stall, and deselect timing parameters -10* -11** -12 symbol min max min max min max units t khqx 3.0 3.0 3.0 ns t khqz 5.0 5.0 5.0 ns *the -10 speed grade available for 2.5v v dd and i/o only. **the -11 speed grade available for 3.3v v dd and i/o only. 27 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs ieee 1149.1 serial boundary scan (jtag) the 18mb sram incorporates a serial boundary scan test access port (tap). this port operates in accordance with ieee standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specification are excluded be- cause their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec-standard 2.5v i/o logic levels. the sram contains a tap controller, instruction reg- ister, boundary scan register, bypass register, and id register. disabling the jtag feature these pins/balls can be left floating (unconnected), if the jtag function is not to be implemented. upon power- up, the device will come up in a reset state which will not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin/ball unconnected if the tap is not used. the pin/ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin/ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the in- struction register, see figure 5 . tdi is internally pulled up and can be unconnected if the tap is unused in an appli- cation. tdi is connected to the most significant bit (msb) of any register. (see figure 6 .) figure 5 tap controller state diagram note: the 0/1 next to each state represents the value of tms at the rising edge of tck. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register* 0 1 2 . . x . . . selection circuitry selection circuitry tck tms tap controller tdi tdo *x = 52 for the x18 configuration, x = 67 for the x32 configuration, x = 71 for the x36 configuration. figure 6 tap controller block diagram 28 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs test data-out (tdo) the tdo output pin/ball is used to serially clock data- out from the registers. the output is active depending upon the current state of the tap state machine. (see figure 5 .) the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see figure 6 .) performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins/balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins/balls as shown in figure 5 . upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through reg- isters, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo pins/balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional pins/balls on the sram. the x36 configuration has a 71-bit-long register, the x32 configu- ration has a 67-bit-long register, and the x18 configura- tion has a 52-bit-long register. the boundary scan register is loaded with the con- tents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift- dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the pins on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32- bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three- bit instruction register. all combinations are listed in the instruction codes table. three of these instructions are listed as reserved and should not be used. the other five instructions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address, data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it performs a capture of the i/o ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins/balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. 29 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs the tap controller does recognize an all-0 instruc- tion. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/ preload instruction has been loaded. there is one dif- ference between the two instructions. unlike the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins/balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruc- tion register upon power-up or whenever the tap con- troller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins/ balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruc- tion. the preload portion of this instruction is not implemented, so the device tap controller is not fully 1149.1-compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirectional pins/balls is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller?s capture setup plus hold time ( t cs plus t ch). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruc- tion register and the tap is placed in a shift-dr state, the bypass register is placed between tdi and tdo. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are con- nected together on a board. reserved these instruction are not implemented but are re- served for future use. do not use these instructions. 30 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs t tlth test clock (tck) 123456 test mode select (tms) t thtl test data-out (tdo) t thth test data-in (tdi) t thmx t mvth t thdx t dvth t tlox t tlov don?t care undefined tap timing tap ac electrical characteristics (notes 1, 2) (0oc t a + 70oc; +2.4v v dd +2.6v) description symbol min max units clock clock cycle time t thth 100 ns clock frequency f tf 10 mhz clock high time t thtl 40 ns clock low time t tlth 40 ns output times tck low to tdo unknown t tlox 0 ns tck low to tdo valid t tlov 20 ns tdi valid to tck high t dvth 10 ns tck high to tdi invalid t thdx 10 ns setup times tms setup t mvth 10 ns capture setup t cs 10 ns hold times tms hold t thmx 10 ns capture hold t ch 10 ns note: 1. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 2. test conditions are specified using the load in figure 7. 31 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs tap ac test conditions input pulse levels ...................................... v ss to 2.5v input rise and fall times ....................................... 1ns input timing reference levels ........................... 1.25v output reference levels .................................... 1.25v test load termination supply voltage .............. 1.25v tdo 1.25v 20pf z = 50 ? o 50 ? figure 7 tap ac output load equivalent 3.3v v dd , tap dc electrical characteristics and operating conditions (0oc t a + 70oc; +3.135v v dd +3.465v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage v ih 2.0 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.8 v 1, 2 input leakage current 0v v in v dd il i -5.0 5.0 a output leakage current output(s) disabled, il o -5.0 5.0 a 0v v in v dd q (dqx) output low voltage i olc = 100a v ol 1 0.7 v 1 output low voltage i olt = 2ma v ol 2 0.8 v 1 output high voltage i ohc = 100a v oh 1 2.9 v 1 output high voltage i oht = 2ma v oh 2 2.0 v 1 note: 1. all voltages referenced to v ss (gnd). 2. overshoot: v ih (ac) v dd + 1.5v for t t khkh/2 undershoot: v il (ac) -0.5v for t t khkh/2 power-up: v ih +2.6v and v dd 2.4v and v dd q 1.4v for t 200ms during normal operation, v dd q must not exceed v dd . control input signals (such as ld#, r/w#, etc.) may not have pulse widths less than t khkl (min) or operate at frequencies exceeding f kf (max). 2.5v v dd , tap dc electrical characteristics and operating conditions (0oc t a + 70oc; +2.4v v dd +2.6v unless otherwise noted) description conditions symbol min max units notes input high (logic 1) voltage v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -5.0 5.0 a output leakage current output(s) disabled, il o -5.0 5.0 a 0v v in v dd q (dqx) output low voltage i olc = 100a v ol 1 0.2 v 1 output low voltage i olt = 2ma v ol 2 0.7 v 1 output high voltage i ohc = 100a v oh 1 2.1 v 1 output high voltage i oht = 2ma v oh 2 1.7 v 1 32 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs identification register definitions instruction field 512k x 18 description revision number xxxx reserved for version number. (31:28) device depth 00111 defines depth of 512k or 1mb words. (27:23) device width 00011 defines width of 18, 32, or 36 bits. (22:18) micron device id xxxxxx reserved for future use. (17:12) micron jedec id 00000101100 allows unique identification of sram vendor. code (11:1) id register presence 1 indicates the presence of an id register. indicator (0) scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan x18: 52 x32: 67 x36: 71 instruction codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1-compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations. 33 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs 165-ball fbga boundary scan order (x18) 27 clk 6b 28 ce2# 6a 29 bwa# 5b 30 bwb# 4a 31 ce2 3b 32 ce# 3a 33 sa 2a 34 sa 2b 35 dqb 2d 36 dqb 2e 37 dqb 2f 38 dqb 2g 39 v ss 1h 40 dqb 1j 41 dqb 1k 42 dqb 1l 43 dqb 1m 44 dqpb 1n 45 mode (lbo#) 1r 46 sa 3p 47 sa 3r 48 sa 4p 49 sa 4r 50 sa1 6p 51 sa0 6r fbga bit# signal name ball id fbga bit# signal name ball id 1 sa 8p 2 sa 9r 3 sa 9p 4 sa 10r 5 sa 10p 6 sa 11r 7 sa 8r 8 dqa 10m 9 dqa 10l 10 dqa 10k 11 dqa 10j 12 zz 11h 13 dqa 11g 14 dqa 11f 15 dqa 11e 16 dqa 11d 17 dqpa 11c 18 sa 11a 19 sa 10b 20 sa 10a 21 sa 9a 22 sa 9b 23 adv/ld# 8a 24 oe# (g#) 8b 25 cke# 7a 26 r/w# 7b 34 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs 165-ball fbga boundary scan order (x32) 34 ce2# 6a 35 bwa# 5b 36 bwb# 5a 37 bwc# 4a 38 bwd# 4b 39 ce2 3b 40 ce# 3a 41 sa 2a 42 sa 2b 43 dqc 1d 44 dqc 1e 45 dqc 1f 46 dqc 1g 47 dqc 2d 48 dqc 2e 49 dqc 2f 50 dqc 2g 51 v ss 1h 52 dqd 1j 53 dqd 1k 54 dqd 1l 55 dqd 1m 56 dqd 2j 57 dqd 2k 58 dqd 2l 59 dqd 2m 60 mode (lbo#) 1r 61 sa 3p 62 sa 3r 63 sa 4p 64 sa 4r 65 sa1 6p 66 sa0 6r fbga bit# signal name ball id fbga bit# signal name ball id 1 sa 8p 2 sa 9r 3 sa 9p 4 sa 10r 5 sa 10p 6 sa 11r 7 sa 8r 8 dqa 11m 9 dqa 11l 10 dqa 11k 11 dqa 11j 12 dqa 10m 13 dqa 10l 14 dqa 10k 15 dqa 10j 16 zz 11h 17 dqb 11g 18 dqb 11f 19 dqb 11e 20 dqb 11d 21 dqb 10g 22 dqb 10f 23 dqb 10e 24 dqb 10d 25 sa 10b 26 sa 10a 27 sa 9a 28 sa 9b 29 adv/ld# 8a 30 oe# (g#) 8b 31 cke# 7a 32 r/w# 7b 33 clk 6b 35 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs 165-ball fbga boundary scan order (x36) 36 ce2# 6a 37 bwa# 5b 38 bwb# 5a 39 bwc# 4a 40 bwd# 4b 41 ce2 3b 42 ce# 3a 43 sa 2a 44 sa 2b 45 nf/ dqpc 1c 46 dqc 1d 47 dqc 1e 48 dqc 1f 49 dqc 1g 50 dqc 2d 51 dqc 2e 52 dqc 2f 53 dqc 2g 54 v ss 1h 55 dqd 1j 56 dqd 1k 57 dqd 1l 58 dqd 1m 59 dqd 2j 60 dqd 2k 61 dqd 2l 62 dqd 2m 63 nf/ dqpd 1n 64 mode (lbo#) 1r 65 sa 3p 66 sa 3r 67 sa 4p 68 sa 4r 69 sa1 6p 70 sa0 6r fbga bit# signal name ball id fbga bit# signal name ball id 1 sa 8p 2 sa 9r 3 sa 9p 4 sa 10r 5 sa 10p 6 sa 11r 7 sa 8r 8 nf/ dqpa 11n 9 dqa 11m 10 dqa 11l 11 dqa 11k 12 dqa 11j 13 dqa 10m 14 dqa 10l 15 dqa 10k 16 dqa 10j 17 zz 11h 18 dqb 11g 19 dqb 11f 20 dqb 11e 21 dqb 11d 22 dqb 10g 23 dqb 10f 24 dqb 10e 25 dqb 10d 26 nf/ dqpb 11c 27 sa 10b 28 sa 10a 29 sa 9a 30 sa 9b 31 adv/ld# 8a 32 oe# (g#) 8b 33 cke# 7a 34 r/w# 7b 35 clk 6b 36 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs 100-pin plastic tqfp (jedec lqfp) 14.00 0.10 1.40 0.05 16.00 0.20 0.10 +0.10 -0.05 0.15 +0.03 -0.02 22.10 +0.10 -0.20 0.32 +0.06 -0.10 20.10 0.10 0.65 typ 0.625 (typ) 1.60 max detail a see detail a 0.60 0.15 1.00 typ gage plane 0.10 0.10 pin #1 id note: 1. all dimensions in millimeters max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 37 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs 165-ball fbga note: 1. all dimensions in millimeters max or typical where noted. min 10.00 14.00 15.00 0.10 1.00 typ 1.00 typ 5.00 0.05 13.00 0.10 pin a1 id pin a1 id ball a1 mold compound: epoxy novolac substrate: plastic laminate 6.50 0.05 7.00 0.05 7.50 0.05 1.20 max solder ball material: eutectic 63% sn, 37% pb solder ball pad: ? .33mm solder ball diameter refers to post reflow condition. the pre-reflow diameter is ? 0.40 seating plane 0.85 0.075 0.12 c c 165x ? 0.45 ball a11 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron, the m and micron logos are trademarks and/or servicemarks of micron technology, inc. zbt and zero bus turnaround are trademarks of integrated device technology, inc., and the architecture is supported by micron technology, inc., and motorola inc. data sheet designation no marking this data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 38 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram micron technology, inc., reserves the right to change products or specifications without notice. mt55l1my18f_h.p65 ? rev. g, pub. 6/02 ?2002, micron technology, inc. 18mb: 1 meg x 18, 512k x 32/36 flow-through zbt sram not recommended for new designs revision history rev. h, pub. 9/02 ............................................................................................................................... ................................. sept/02 updated operating temperature range: from +10oc t j +110oc to 0oc t a +70oc rev. g, pub. 6/02 ............................................................................................................................... ................................. june/02 added ?not recommended for new designs? to header rev. f, pub. 3/02 ............................................................................................................................... ................................... mar/02 removed 119-pin pbga and references removed advance designation updated operating temperature range: from 0oc t a +70oc to +10oc t j +110oc removed -8.8 speed grade from 2.5 v dd and i/o removed -10 speed grade from 3.3 v dd and i/o rev. e, pub. 1/02, advance ............................................................................................................................... ............... jan/02 changed max temperature from +70oc to +110oc updated 100-pin tqfp capacitance values: c i from typ 3pf, max 4pf to typ 4.8pf, max 6.0pf c o from typ 4pf, max 5pf to typ 3.8pf, max 4.5pf c a from typ 3pf, max 3.5pf to typ 4.7pf, max 5.5pf c ck from typ 3pf, max 3.5pf to typ 4.5pf, max 5.0pf rev. d, pub. 9/01, advance ............................................................................................................................... ............. sept/01 removed -11 speed grade from 3.3 v dd and i/o rev. c, pub. 9/01, advance ............................................................................................................................... ............. sept/01 removed industrial temperature references changed i dd tables by splitting x18 and x32/36 configuration changed nc references to nf removed note ?not recommended for new design? from 119-pin fbga changed boundary scan order, 165-ball fbga, x18 and x32/36 8p (sa) moved to bit #7 from bit #1 increased i dd table values rev. 3/01, advance ............................................................................................................................... ................. march/19/01 added industrial temperature note and references changed 16mb to 18mb references added -8.8 speed grades rev. 1/01, advance ............................................................................................................................... ........................ jan/9/01 added 165-ball jtag boundary scan added 119-pin pbga package and references rev. 8/00, advance ............................................................................................................................... ..................... aug/22/00 removed fbga part marking guide rev. 7/00, advance ............................................................................................................................... ....................... aug/8/00 changed fbga capacitance values c i ; typ 2.5 pf from 4 pf; max 3.5 pf from 5 pf c o ; typ 4 pf from 6 pf; max 5 pf from 7 pf c ck ; typ 2.5 pf from 5 pf; max 3.5 pf from 6 pf rev. 7/00, advance ............................................................................................................................... ...................... jun/28/00 added 165-pin fbga package added fbga part marking references removed 119-pin pbga and references rev. 4/00, advance ............................................................................................................................... ...................... apr/13/00 added note: zz has internal pull-down rev. 3/00, advance ............................................................................................................................... ........................ apr/6/00 updated boundary scan order rev. 1/00, advance ............................................................................................................................... ...................... jan/18/00 added bga jtag functionality added 119-pin pbga package added advance status original document, rev. 11/99, draft ..................................................................................................................... no v/11/99 |
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